Resistivity

Resistivity is a physical quantity describing the inherent resistance characteristic of a material. By definition, the resistivity of a material numerically equals the resistance of a conductor made from that material with a length of 1 meter and a cross-sectional area of 1 square meter. Its unit is Ω·m; Ω·cm is commonly adopted in the semiconductor industry.

For silicon semiconductor materials, resistivity follows the formula:

\(\rho = \frac{1}{nq\mu}\) where n stands for carrier concentration, q for electric charge quantity, and \(\mu\) for carrier mobility. In other words, the resistivity of silicon depends on the concentration and mobility of internal electrons and holes, and is independent of the material’s size and geometry.

In practical applications, Silicon Wafers are generally categorized into high-resistivity silicon and low-resistivity silicon. High-resistivity silicon features extremely low impurity concentration (typically below \(10^{12}\ \mathrm{cm^{-3}}\)) with a resistivity ranging from \(10^3\) to \(10^6\ \Omega\cdot\mathrm{cm}\). Conventional electronic-grade silicon produced via Czochralski (CZ) or Float-Zone (FZ) methods usually has a resistivity of 1 to \(20\ \Omega\cdot\mathrm{cm}\), corresponding to a doping concentration of roughly \(10^{14}\) to \(10^{16}\ \mathrm{cm^{-3}}\).

Fabrication of high-resistivity silicon demands ultra-high material purity. Two mainstream manufacturing techniques are Float-Zone (FZ) and Czochralski (CZ) methods. The Float-Zone process melts a narrow segment of a polysilicon rod with a high-frequency heater and slowly shifts the molten zone to achieve repeated purification via impurity segregation. Free of contamination from quartz crucibles, it yields high-purity silicon with resistivity exceeding \(10{,}000\ \Omega\cdot\mathrm{cm}\). In contrast, conventional Czochralski silicon suffers from oxygen impurities (around \(10^{18}\ \mathrm{cm^{-3}}\)) introduced by contact between the crucible and silicon melt, limiting its maximum resistivity to below \(1{,}000\ \Omega\cdot\mathrm{cm}\). Note that the resistivity of many commercially specified high-resistivity silicon wafers will degrade to a certain extent after annealing.

Beyond doping concentration, temperature exerts a prominent impact on silicon resistivity, which varies across three characteristic temperature regimes:

1. Low-temperature range

   Rising temperature enhances impurity ionization and increases carrier concentration, leading to reduced resistivity.

2. Room-temperature range

   Impurities are nearly fully ionized while intrinsic excitation remains negligible. Strengthened lattice vibration lowers carrier mobility, so resistivity rises with temperature.

3. High-temperature range dominated by intrinsic excitation

   Massive intrinsic carriers are generated, causing resistivity to drop sharply and behave like intrinsic semiconductors.

This temperature dependence defines the maximum operating temperature of silicon devices, generally around 250°C.

Sheet Resistance

Sheet resistance, often abbreviated as sheet resistance, refers to the resistance of a thin film per unit square area, calculated as resistivity divided by film thickness, with the unit Ω/□ (ohms per square). A core property of sheet resistance is that the resistance between opposite edges of any square piece of the thin film remains identical, regardless of side length—whether 1 meter or 1 millimeter.

The concept of sheet resistance was primarily developed for thin-film structures and plays a unique role in MEMS device design. Analogous to square building blocks, total resistance can be directly calculated once sheet resistance is known by multiplying it by the number of square segments, determined by the length-to-width ratio of the conductive path:

\(R_\mathrm{total} = R_\mathrm{sq} \times \frac{L}{W}\)

This practical convenience delivers remarkable benefits in manufacturing processes. For polysilicon thin films or ion-implanted silicon layers, circuit designers and process engineers can complete circuit design merely by measuring sheet resistance, without precise knowledge of implantation depth (junction depth). This greatly streamlines communication and collaboration between design and manufacturing teams.